Samsung 3nm MBCFET Chip

Samsung 3nm MBCFET Chip

At the IEEE International Solid-State Circuits Conference (ISSCC), Samsung shared the manufacturing details of the upcoming 3nm GAE MBCFET chip.

3nm MBCFET chip: performance, density, and power consumption

In the upcoming 3nm manufacturing process, Samsung’s fab will become the first semiconductor manufacturer to start using GAAFET style structures. Although this node has not yet arrived, Samsung’s engineers shared about the upcoming 3nm multi-bridge channel FET (multi-bridge channel FET, GAE MBCFET) some details of manufacturing technology.

Different chip manufacturing processes

GAAFET style structures

There are two types of GAAFETs: one is a typical GAAFET, called a nanowire, with “thin” fins, and the other is an MBCFET, called a nanosheet, which uses “thick” fins. In both cases, the gate material wraps the channel region in all directions. The actual implementation of nanowires and nanosheets depends largely on the design, so many industry observers use the same term “GAAFET” to describe both.

GAAFET first appeared in 1988, so the key advantages of this technology are already widely known. The special structure of this transistor allows designers to precisely adjust them by adjusting the channel width (also known as effective width) of the transistors to achieve high performance or low power consumption. Wider flakes can achieve higher performance at higher power, while thinner/narrower flakes can reduce power consumption and performance. In order to do similar things on fin field-effect transistors (FinFETs), engineers have to use additional fins to improve performance. But in this case, the “width” of the transistor channel can only be doubled or tripled, which is not accurate. In addition, GAAFET adjustment allows increasing transistor density, because different transistors can be used for different purposes.

As early as 2019, version 0.1 of Samsung’s 3GAE process design kit included four different nanosheet widths, providing early adopters with a certain degree of flexibility. It is not clear whether they have added more widths to increase flexibility. Samsung said that compared with 7LPP technology, its 3GAE node will increase performance by 30%, and reduce power consumption by 50%. And the transistor density has increased by 80%.


Samsung introduced its 256Mb MBCFET SRAM chip on ISSCC, the chip size is 56mm. This means that although the company has not yet launched its first 3GAE logic chip, it is clear that the technology is applicable to SRAM.

SRAM is a six-transistor memory cell: two transmission gates, two pull-up gates, and two pull-down gates. In the FinFET design, SRAM cells use the same transistors with the same channel width. On the MBCFET, Samsung can adjust the channel width, so it proposes two solutions. In one case, it uses a transistor with a wider channel as the transmission gate and pull-down gate. In the other case, it will use a transistor with a wider channel as a transmission gate and a transistor with a narrower channel as a pull-down gate. According to an IEEE Spectrum report, Samsung stated that compared with conventional SRAM cells, Samsung has successfully reduced the write voltage by using transistors with a wider channel for the transfer gate and transistors with a narrower channel for the pull-up. Up to 230 mV.

Research and development of 3nm process technology

Both Samsung and TSMC have started the research and development of 3nm process technology. Now the former has begun to show some 3nm process technical content to the outside world. At the IEEE International Solid-State Circuits Conference, Samsung shared the manufacturing details of the 3nm GAE MBCEFET chip with participants.

Samsung introduced the principles of the GAE process in 2019. It announced that it would invest 133 trillion won in the logic chip business, including the foundry business. In the next 10 years, it would surpass TSMC and become the world’s largest chip foundry. In addition, compared to the 7LPP process, the GAE process can achieve a 30% performance improvement, a 50% reduction in power consumption, and an 80% increase in transistor density.

Samsung will launch3GAE (its first-generation MBCFET technology) in 2022. Therefore, Samsung has not yet disclosed all its features. The company discussed at ISSCC how to use new transistors to improve the performance and scalability of SRAM. In recent years, the scalability of SRAM has been lagging behind the scalability of logic. Modern system-on-chips (SoC) use a load of SRAM for various caches, so improving its scalability is a vital task.

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